The present invention is directed to a test device and method, and more particularly to a test device and method for testing the susceptibility to failure of a functional circuit implemented in a semiconductor chip.
Over the past several years semiconductor chips have become the basis of nearly all modern electronic devices. For example, modern computers employ various processing chips to implement their function. Such computer chips are increasingly employing larger numbers of basic components, such as transistors, in order to improve both performance and processing capability of the computer chip. In order to increase the number of components used, it is necessary to increase the integration of the devices on the chip. Higher integration can be achieved by reducing the number of components needed to implement a desired function and by packing the individual components closer together. As more individual components are placed on a single chip the overall production cost is reduced.
Various approaches have been used to implement different functionality on a chip. For example, precharged dynamic logic circuits have been increasingly employed to implement logic functionality in modern computer chips. Dynamic logic is desirable because of its small size and fast performance. One drawback associated with using dynamic logic circuits is that such circuits tend to be quite sensitive to noise and other influences arising on the chip. External influences, such as noise and crosstalk introduced from other circuitry on the chip located in the vicinity of the dynamic logic circuit, must be carefully considered in designing chips using dynamic logic circuits.
The problems associated with the external influences on the operation of the dynamic logic circuitry becomes even more significant when the density of the components used to form the circuitry is increased. For example, where a number of dynamic logic circuits are grouped together in the same horizontal plane of the chip, the adjacent circuits may have a significant influence on each other. One notable problem involves signal wiring of such circuitry. If relatively long coupling lengths are used in the wiring layer, significant portions of the wiring may lie adjacent to wiring associated with one or more other circuits. A charge associated with a signal on an adjacent line may be capacitively coupled to the wiring of an adjacent dynamic circuit. The amount of voltage capacitively coupled onto a given line depends on the spacing between the adjacent wiring and on the coupling length because longer coupling lengths tend to increase the amount of adjacent wiring. As the spacing between the adjacent wiring decreases the amount of capacitively coupled voltage increases. A large enough voltage capacitively coupled to a wiring line of a dynamic circuit will cause undesirable switching in the dynamic circuit causing the chip to fail.
In order to prevent external influences, such as capacitively coupled voltages, from adversely affecting the operation of horizontally adjacent dynamic circuits, design specifications must be made in consideration of the potential external influences. For example, the dynamic circuits may be designed using components which are more noise resistant. One such approach is to provide a large, noise resistant pull-up transistor in a half latch of the dynamic logic circuit to maintain a desired voltage on a precharge node of the dynamic logic circuit despite the presence of capacitively coupled voltages which cause leakage through a control transistor. This approach, however, reduces the performance of the circuit because the large pull-up transistor also resists desired switching operations making it more difficult to switch the dynamic logic circuit during normal operation.
Another technique employed to avoid failure as a result of influences on the chip from devices external to the dynamic logic circuitry is to prescribe conservative horizontal wiring rules to ensure that crosstalk, for example, does not exceed acceptable levels for the components used in the dynamic circuitry. Such rules include prescribing an acceptable pitch or spacing between adjacent lines and an acceptable coupled length for the design.
A problem with such an approach is that conservative guidelines must account for potential deviations, from the ideal design parameters, which occur during the actual manufacturing process of the device. For example, for a given design using selected components it may be necessary to avoid a spacing between two 1.0 micron wide lines of less than 1.0 micron. This constraint may be necessary to avoid excessive capacitive coupling between the two lines. If manufacturing process limitations indicated that the actual line width can vary as much as 0.25 microns, then a designer must prescribe a spacing between the wiring lines of 1.5 microns to ensure that the required 1.0 micron spacing is present in circuits exhibiting the worst case process deviations, that is, two adjacent wiring lines each formed 1.25 microns wide. While such large process deviations may occur in only a very small percentage of the produced chips, the conservative design is required to ensure that none of the chips fail. As can be appreciated, such conservative design specifications significantly increase the overall size of the chip.
As the above example illustrates, when the process limitations are taken into account extremely conservative guidelines must be imposed in the manufacturing process to prevent shipment of bad chips. This problem becomes even more pronounced when the worst case scenario is concurrently extended to include the maximum potential deviations for each variable and component in the design.
The above approach severely hampers the design of chips using larger numbers of small, fast devices. Accordingly, there exists a need to provide a mechanism allowing aggressive design using, for example, precharged dynamic logic circuitry, while ensuring any failure arising as a result of process limitations can be detected in chips manufactured using the aggressive design.